diff options
| author | Andrew Bresticker <abrestic@chromium.org> | 2014-09-18 14:47:16 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 07:44:54 +0100 |
| commit | dfc94d1b21520093b7b6788ab25c955456ad4493 (patch) | |
| tree | 0e8862637ff266bea99f4e15bcdb36832a0c742e /arch/mips/include/asm | |
| parent | d8725fddfd913129d58f126650afdabebd84d3ca (diff) | |
| download | linux-stable-dfc94d1b21520093b7b6788ab25c955456ad4493.tar.gz linux-stable-dfc94d1b21520093b7b6788ab25c955456ad4493.tar.bz2 linux-stable-dfc94d1b21520093b7b6788ab25c955456ad4493.zip | |
MIPS: sead3: Do not overlap CPU/GIC IRQ ranges
In preparation for GIC IRQ domain support, assign a GIC IRQ base
that does not overlap with the CPU IRQs.
Note that this breaks SEAD-3 when the GIC is in EIC mode, though
I'm not convinced it was working before either. It will be fixed
in the following patches.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7813/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mips-boards/sead3int.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h index 6b17aaf7d901..2320331f1464 100644 --- a/arch/mips/include/asm/mips-boards/sead3int.h +++ b/arch/mips/include/asm/mips-boards/sead3int.h @@ -14,6 +14,6 @@ #define GIC_BASE_ADDR 0x1b1c0000 #define GIC_ADDRSPACE_SZ (128 * 1024) -#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 0) +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) #endif /* !(_MIPS_SEAD3INT_H) */ |