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author | Olof Johansson <olof@lixom.net> | 2013-08-29 19:12:04 -0700 |
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committer | Olof Johansson <olof@lixom.net> | 2013-08-29 19:12:04 -0700 |
commit | 2bbc31ef2b398d17016c6438016cc76913990950 (patch) | |
tree | 10de572013948341054d73acfab0f6d77ae35cbd /arch/mips/kernel/smp-bmips.c | |
parent | a3e008d1b5e39abe81e233bde623604841ff9a73 (diff) | |
parent | af0721966195b3966214edd54af0d5f84d65419a (diff) | |
download | linux-stable-2bbc31ef2b398d17016c6438016cc76913990950.tar.gz linux-stable-2bbc31ef2b398d17016c6438016cc76913990950.tar.bz2 linux-stable-2bbc31ef2b398d17016c6438016cc76913990950.zip |
Merge tag 'omap-for-v3.12/fixes-non-critical-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
From Tony Lindgren:
Omap fixes for the merge window that are not urgent enough
for the -rc series.
* tag 'omap-for-v3.12/fixes-non-critical-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2: use 'int' instead of 'unsigned' for variable 'gpmc_irq_start'
ARM: OMAP2: remove useless variable 'ret'
ARM: OMAP: dma: fix error return code in omap_system_dma_probe()
ARM: OMAP2+: fix wrong address when loading PRM_FRAC_INCREMENTOR_DENUMERATOR_RELOAD
ARM: OMAP2+: am33xx-restart: trigger warm reset on omap2+ boards
ARM: OMAP2: Use a consistent AM33XX SoC option description
ARM: OMAP2+: Remove legacy device creation for McPDM and DMIC
+ Linux 3.11-rc6
Diffstat (limited to 'arch/mips/kernel/smp-bmips.c')
-rw-r--r-- | arch/mips/kernel/smp-bmips.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index c0bb4d59076a..126da74d4c55 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void) int i, cpu = 1, boot_cpu = 0; #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) + int cpu_hw_intr; + /* arbitration priority */ clear_c0_brcm_cmt_ctrl(0x30); @@ -79,15 +81,13 @@ static void __init bmips_smp_setup(void) * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output - * - * If booting from TP1, leave the existing CMT interrupt routing - * such that TP0 responds to SW1 and TP1 responds to SW0. */ if (boot_cpu == 0) - change_c0_brcm_cmt_intr(0xf8018000, - (0x02 << 27) | (0x03 << 15)); + cpu_hw_intr = 0x02; else - change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27)); + cpu_hw_intr = 0x1d; + + change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15)); /* single core, 2 threads (2 pipelines) */ max_cpus = 2; @@ -202,9 +202,15 @@ static void bmips_init_secondary(void) #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) void __iomem *cbr = BMIPS_GET_CBR(); unsigned long old_vec; + unsigned long relo_vector; + int boot_cpu; + + boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); + relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : + BMIPS_RELO_VECTOR_CONTROL_1; - old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1); - __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1); + old_vec = __raw_readl(cbr + relo_vector); + __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); #elif defined(CONFIG_CPU_BMIPS5000) |