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authorMark Brown <broonie@kernel.org>2020-10-06 16:19:24 +0100
committerMark Brown <broonie@kernel.org>2020-10-06 16:19:24 +0100
commitfd6b519a30a7179026d22c98d6bf10bb5ca8ca27 (patch)
treee4a6bc4d8548a5b8db7148a18eb257b84e72d48b /arch/mips/mm/c-r4k.c
parent43499134f50a77844f0503df2c995f43b858f4c3 (diff)
parent856deb866d16e29bd65952e0289066f6078af773 (diff)
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Merge tag 'v5.9-rc5' into asoc-5.10
Linux 5.9-rc5
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
-rw-r--r--arch/mips/mm/c-r4k.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fc5a6d25f74f..0ef717093262 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1712,7 +1712,11 @@ static void setup_scache(void)
printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
scache_size >> 10,
way_string[c->scache.ways], c->scache.linesz);
+
+ if (current_cpu_type() == CPU_BMIPS5000)
+ c->options |= MIPS_CPU_INCLUSIVE_CACHES;
}
+
#else
if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
panic("Dunno how to handle MIPS32 / MIPS64 second level cache");