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authorPaul Cercueil <paul@crapouillou.net>2021-05-30 18:17:55 +0100
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2021-06-01 11:44:46 +0200
commit1660710cf5d8d44ec351a5df57c35516f1fbf5e0 (patch)
tree591624fadbf915c66cef78f5afc7d5c35ae4833c /arch/mips/mm
parentc8ba52d1b7e317c54d461970e4bdeec10ea1d9c4 (diff)
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MIPS: mm: XBurst CPU requires sync after DMA
I am not sure why this is required, but if this is not enabled, reading from a buffer in which data has been DMA'd may read incorrect values. This used to happen for instance in mmc_app_send_scr() (drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied by the CPU to a different location. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/dma-noncoherent.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 212f3ce75a6b..3c4fc97b9f39 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -32,6 +32,7 @@ static inline bool cpu_needs_post_dma_flush(void)
case CPU_R12000:
case CPU_BMIPS5000:
case CPU_LOONGSON2EF:
+ case CPU_XBURST:
return true;
default:
/*