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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-08-24 18:32:43 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-09-07 22:23:29 +0200
commit802b83627f54d63d3d95d0285ec9a5d80be434c0 (patch)
tree240f728d7f4923617f34fba529157606d5ac9b85 /arch/mips/mm
parent8c2ede45edbea7e970ea6bd171fc6afbec0761b3 (diff)
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MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Use a new config option to enable R4600 V1 index I-cacheop workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/c-r4k.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fc5a6d25f74f..bf454da84a9b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -366,7 +366,8 @@ static void r4k_blast_icache_page_indexed_setup(void)
else if (ic_lsize == 16)
r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
else if (ic_lsize == 32) {
- if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
+ cpu_is_r4600_v1_x())
r4k_blast_icache_page_indexed =
blast_icache32_r4600_v1_page_indexed;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
@@ -394,7 +395,8 @@ static void r4k_blast_icache_setup(void)
else if (ic_lsize == 16)
r4k_blast_icache = blast_icache16;
else if (ic_lsize == 32) {
- if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
+ if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
+ cpu_is_r4600_v1_x())
r4k_blast_icache = blast_r4600_v1_icache32;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache = tx49_blast_icache32;