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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2024-02-09 18:07:47 +0000 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-02-20 12:41:51 +0100 |
| commit | a77dabc8e8e4686f542f35e9e3ef09310b018b23 (patch) | |
| tree | b0338f4861ac9713767aea1171ae5679d4710c22 /arch/mips/mm | |
| parent | b401b621758e46812da61fa58a67c3fd8d91de0d (diff) | |
| download | linux-stable-a77dabc8e8e4686f542f35e9e3ef09310b018b23.tar.gz linux-stable-a77dabc8e8e4686f542f35e9e3ef09310b018b23.tar.bz2 linux-stable-a77dabc8e8e4686f542f35e9e3ef09310b018b23.zip | |
MIPS: Unify define of CP0 registers for uasm code
Definitions of uasm variant of CP0 registers are unified to
mipsregs.h, so they lay together with uasm variant of
the code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/tlbex.c | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4017fa0e2f68..c9d00d9cb3c8 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -32,6 +32,7 @@ #include <asm/cacheflush.h> #include <asm/cpu-type.h> +#include <asm/mipsregs.h> #include <asm/mmu_context.h> #include <asm/uasm.h> #include <asm/setup.h> @@ -280,23 +281,6 @@ static inline void dump_handler(const char *symbol, const void *start, const voi #define K0 26 #define K1 27 -/* Some CP0 registers */ -#define C0_INDEX 0, 0 -#define C0_ENTRYLO0 2, 0 -#define C0_TCBIND 2, 2 -#define C0_ENTRYLO1 3, 0 -#define C0_CONTEXT 4, 0 -#define C0_PAGEMASK 5, 0 -#define C0_PWBASE 5, 5 -#define C0_PWFIELD 5, 6 -#define C0_PWSIZE 5, 7 -#define C0_PWCTL 6, 6 -#define C0_BADVADDR 8, 0 -#define C0_PGD 9, 7 -#define C0_ENTRYHI 10, 0 -#define C0_EPC 14, 0 -#define C0_XCONTEXT 20, 0 - #ifdef CONFIG_64BIT # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) #else |