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| author | Serge Semin <fancer.lancer@gmail.com> | 2024-02-26 13:54:22 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-03-11 14:02:15 +0100 |
| commit | 732932220078f6312f3ef57c17523d3d7f995655 (patch) | |
| tree | e5b90dd7cf5ae793ffec485441345d5482087db1 /arch/mips | |
| parent | 8bc8db2ab2832daabdd06feeabdd511dc9575bb6 (diff) | |
| download | linux-stable-732932220078f6312f3ef57c17523d3d7f995655.tar.gz linux-stable-732932220078f6312f3ef57c17523d3d7f995655.tar.bz2 linux-stable-732932220078f6312f3ef57c17523d3d7f995655.zip | |
mips: cm: Convert __mips_cm_phys_base() to weak function
Based on the design pattern utilized in the CM GCR base address getter
implementation, the platform-specific code is capable to re-define the
getter and re-use the weakly defined initial version. But since the
pattern hasn't been used for over 10 years and another similar case (CM
L2-sync only base address getter) has just been fixed, let's unify the
interface and convert it to a more traditional single weakly defined
method: mips_cm_phys_base() (see the link below for the discussion around
this).
Link: https://lore.kernel.org/linux-mips/20240215171740.14550-3-fancer.lancer@gmail.com
Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/mips-cm.h | 7 | ||||
| -rw-r--r-- | arch/mips/kernel/mips-cm.c | 5 |
2 files changed, 4 insertions, 8 deletions
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 6d132b537f6d..c2930a75b7e4 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -22,16 +22,15 @@ extern void __iomem *mips_gcr_base; extern void __iomem *mips_cm_l2sync_base; /** - * __mips_cm_phys_base - retrieve the physical base address of the CM + * mips_cm_phys_base - retrieve the physical base address of the CM * * This function returns the physical base address of the Coherence Manager * global control block, or 0 if no Coherence Manager is present. It provides * a default implementation which reads the CMGCRBase register where available, * and may be overridden by platforms which determine this address in a - * different way by defining a function with the same prototype except for the - * name mips_cm_phys_base (without underscores). + * different way by defining a function with the same prototype. */ -extern phys_addr_t __mips_cm_phys_base(void); +extern phys_addr_t mips_cm_phys_base(void); /** * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 268ac0b811e3..3a115fab5573 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -179,7 +179,7 @@ static char *cm3_causes[32] = { static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock); static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); -phys_addr_t __mips_cm_phys_base(void) +phys_addr_t __weak mips_cm_phys_base(void) { unsigned long cmgcr; @@ -198,9 +198,6 @@ phys_addr_t __mips_cm_phys_base(void) return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); } -phys_addr_t mips_cm_phys_base(void) - __attribute__((weak, alias("__mips_cm_phys_base"))); - phys_addr_t __weak mips_cm_l2sync_phys_base(void) { u32 base_reg; |