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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2017-08-08 13:58:50 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-08-10 23:32:09 +1000 |
| commit | 72e4b2cdf07b4c43115f058ed74d694eab5d6454 (patch) | |
| tree | bce21f1e76f78f8843732cdc1c2988f5931891ec /arch/powerpc/boot/util.S | |
| parent | de41ef6e4d70f2d30f96ca959fdde3200403d167 (diff) | |
| download | linux-stable-72e4b2cdf07b4c43115f058ed74d694eab5d6454.tar.gz linux-stable-72e4b2cdf07b4c43115f058ed74d694eab5d6454.tar.bz2 linux-stable-72e4b2cdf07b4c43115f058ed74d694eab5d6454.zip | |
powerpc/time: refactor MFTB() to limit number of ifdefs
The 8xx cannot access the TBL and TBU registers using mfspr/mtspr
It must be accessed using mftb/mftbu
Due to this, there is a number of places with #ifdef CONFIG_8xx
This patch defines new macros MFTBL(x) and MFTBU(x) on the same model
as MFTB(x) and tries to make use of them as much as possible.
In arch/powerpc/include/asm/timex.h, we also remove the ifdef
for the asm() operands as the compiler doesn't mind unused operands
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/boot/util.S')
| -rw-r--r-- | arch/powerpc/boot/util.S | 24 |
1 files changed, 5 insertions, 19 deletions
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S index 243b8497d58b..ec069177d942 100644 --- a/arch/powerpc/boot/util.S +++ b/arch/powerpc/boot/util.S @@ -71,32 +71,18 @@ udelay: add r4,r4,r5 addi r4,r4,-1 divw r4,r4,r5 /* BUS ticks */ -#ifdef CONFIG_8xx -1: mftbu r5 - mftb r6 - mftbu r7 -#else -1: mfspr r5, SPRN_TBRU - mfspr r6, SPRN_TBRL - mfspr r7, SPRN_TBRU -#endif +1: MFTBU(r5) + MFTBL(r6) + MFTBU(r7) cmpw 0,r5,r7 bne 1b /* Get [synced] base time */ addc r9,r6,r4 /* Compute end time */ addze r8,r5 -#ifdef CONFIG_8xx -2: mftbu r5 -#else -2: mfspr r5, SPRN_TBRU -#endif +2: MFTBU(r5) cmpw 0,r5,r8 blt 2b bgt 3f -#ifdef CONFIG_8xx - mftb r6 -#else - mfspr r6, SPRN_TBRL -#endif + MFTBL(r6) cmpw 0,r6,r9 blt 2b 3: blr |