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| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2021-03-12 12:50:11 +0000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-03-29 13:22:03 +1100 |
| commit | 52ae92cc290f0506eef9ad5466bb453ce4a9e80e (patch) | |
| tree | 723d57404fc95babb53520190c272455027be352 /arch/powerpc/include | |
| parent | a58cbed68315111c663f35603a42547f72acd6f8 (diff) | |
| download | linux-stable-52ae92cc290f0506eef9ad5466bb453ce4a9e80e.tar.gz linux-stable-52ae92cc290f0506eef9ad5466bb453ce4a9e80e.tar.bz2 linux-stable-52ae92cc290f0506eef9ad5466bb453ce4a9e80e.zip | |
powerpc/40x: Don't use SPRN_SPRG_SCRATCH0/1 in TLB miss handlers
SPRN_SPRG_SCRATCH5 is used to save SPRN_PID.
SPRN_SPRG_SCRATCH6 is already available.
SPRN_PID is only 8 bits. We have r12 that contains CR.
We only need to preserve CR0, so we have space available in r12
to save PID.
Keep PID in r12 and free up SPRN_SPRG_SCRATCH5.
Then In TLB miss handlers, instead of using SPRN_SPRG_SCRATCH0 and
SPRN_SPRG_SCRATCH1, use SPRN_SPRG_SCRATCH5 and SPRN_SPRG_SCRATCH6
to avoid future conflicts with normal exception prologs.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/4cdaa85d38e14d594ba902424060ec55babf2c42.1615552866.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'arch/powerpc/include')
0 files changed, 0 insertions, 0 deletions