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| author | Nicholas Piggin <npiggin@gmail.com> | 2022-03-03 15:33:15 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2022-05-13 21:34:33 +1000 |
| commit | 2852ebfa10afdcefff35ec72c8da97141df9845c (patch) | |
| tree | feeb10063acba38d59e8f721a9988e6c0816c2c5 /arch/powerpc/kvm/book3s_hv_nested.c | |
| parent | 11681b79b1ab52e7625844d7ce52c4d5201a43b2 (diff) | |
| download | linux-stable-2852ebfa10afdcefff35ec72c8da97141df9845c.tar.gz linux-stable-2852ebfa10afdcefff35ec72c8da97141df9845c.tar.bz2 linux-stable-2852ebfa10afdcefff35ec72c8da97141df9845c.zip | |
KVM: PPC: Book3S HV Nested: L2 LPCR should inherit L1 LPES setting
The L1 should not be able to adjust LPES mode for the L2. Setting LPES
if the L0 needs it clear would cause external interrupts to be sent to
L2 and missed by the L0.
Clearing LPES when it may be set, as typically happens with XIVE enabled
could cause a performance issue despite having no native XIVE support in
the guest, because it will cause mediated interrupts for the L2 to be
taken in HV mode, which then have to be injected.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220303053315.1056880-7-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/kvm/book3s_hv_nested.c')
| -rw-r--r-- | arch/powerpc/kvm/book3s_hv_nested.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c index 75169e0753ce..ce08573fc58f 100644 --- a/arch/powerpc/kvm/book3s_hv_nested.c +++ b/arch/powerpc/kvm/book3s_hv_nested.c @@ -261,8 +261,7 @@ static void load_l2_hv_regs(struct kvm_vcpu *vcpu, /* * Don't let L1 change LPCR bits for the L2 except these: */ - mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD | - LPCR_LPES | LPCR_MER; + mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD | LPCR_MER; /* * Additional filtering is required depending on hardware |