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| author | Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> | 2019-03-28 17:10:33 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2019-04-20 22:02:26 +1000 |
| commit | c9d8dda42372dce00ac3a1c653bef7b8d2dbe3ce (patch) | |
| tree | 31d44b16b12cdba6f861a368f57f9196a4fd344d /arch/powerpc/platforms/pseries/ras.c | |
| parent | 56c46bba9bbfe229b4472a5be313c44c5b714a39 (diff) | |
| download | linux-stable-c9d8dda42372dce00ac3a1c653bef7b8d2dbe3ce.tar.gz linux-stable-c9d8dda42372dce00ac3a1c653bef7b8d2dbe3ce.tar.bz2 linux-stable-c9d8dda42372dce00ac3a1c653bef7b8d2dbe3ce.zip | |
powerpc/pseries/mce: Improve array initialization.
This is a follow up to the patch that fixed misleading print for TLB
mutlihit due to wrongly populated mc_err_types[] array. Convert all the
static array initialization to '[x] = val' style for better
readability of array indexing and avoid any further confusion.
Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/platforms/pseries/ras.c')
| -rw-r--r-- | arch/powerpc/platforms/pseries/ras.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c index 452dcfd7e5dd..a25c2ac0c9c0 100644 --- a/arch/powerpc/platforms/pseries/ras.c +++ b/arch/powerpc/platforms/pseries/ras.c @@ -539,44 +539,44 @@ static void pseries_print_mce_info(struct pt_regs *regs, int disposition = rtas_error_disposition(errp); static const char * const initiators[] = { - "Unknown", - "CPU", - "PCI", - "ISA", - "Memory", - "Power Mgmt", + [0] = "Unknown", + [1] = "CPU", + [2] = "PCI", + [3] = "ISA", + [4] = "Memory", + [5] = "Power Mgmt", }; static const char * const mc_err_types[] = { - "UE", - "SLB", - "ERAT", - "Unknown", - "TLB", - "D-Cache", - "Unknown", - "I-Cache", + [0] = "UE", + [1] = "SLB", + [2] = "ERAT", + [3] = "Unknown", + [4] = "TLB", + [5] = "D-Cache", + [6] = "Unknown", + [7] = "I-Cache", }; static const char * const mc_ue_types[] = { - "Indeterminate", - "Instruction fetch", - "Page table walk ifetch", - "Load/Store", - "Page table walk Load/Store", + [0] = "Indeterminate", + [1] = "Instruction fetch", + [2] = "Page table walk ifetch", + [3] = "Load/Store", + [4] = "Page table walk Load/Store", }; /* SLB sub errors valid values are 0x0, 0x1, 0x2 */ static const char * const mc_slb_types[] = { - "Parity", - "Multihit", - "Indeterminate", + [0] = "Parity", + [1] = "Multihit", + [2] = "Indeterminate", }; /* TLB and ERAT sub errors valid values are 0x1, 0x2, 0x3 */ static const char * const mc_soft_types[] = { - "Unknown", - "Parity", - "Multihit", - "Indeterminate", + [0] = "Unknown", + [1] = "Parity", + [2] = "Multihit", + [3] = "Indeterminate", }; if (!rtas_error_extended(errp)) { |