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| author | David S. Miller <davem@sunset.davemloft.net> | 2007-10-02 01:03:09 -0700 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-02 01:03:09 -0700 |
| commit | 25e5566ed38650f7990041fcd20571d6ddd2a040 (patch) | |
| tree | 26d5bf006a6945930102fa01ad0edcd479b39bbf /arch/powerpc/platforms/pseries/xics.c | |
| parent | 8cc8c28a9acdceda0e60519167a052cc3408c5c3 (diff) | |
| download | linux-stable-25e5566ed38650f7990041fcd20571d6ddd2a040.tar.gz linux-stable-25e5566ed38650f7990041fcd20571d6ddd2a040.tar.bz2 linux-stable-25e5566ed38650f7990041fcd20571d6ddd2a040.zip | |
[SPARC64]: Fix missing load-twin usage in Niagara-1 memcpy.
For the case where the source is not aligned modulo 8
we don't use load-twins to suck the data in and this
kills performance since normal loads allocate in the
L1 cache (unlike load-twin) and thus big memcpys swipe
the entire L1 D-cache.
We need to allocate a register window to implement this
properly, but that actually simplifies a lot of things
as a nice side-effect.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/powerpc/platforms/pseries/xics.c')
0 files changed, 0 insertions, 0 deletions