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author | Reza Arbab <arbab@linux.ibm.com> | 2018-08-02 23:03:36 -0500 |
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committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-08-03 20:09:01 +1000 |
commit | 9eab9901b015f489199105c470de1ffc337cfabb (patch) | |
tree | cd796488a9a1d0fc47526f3f3e19c904c2697452 /arch/powerpc/tools/checkpatch.sh | |
parent | 06832fc004815b4b43628d21fc81715e8e7cadff (diff) | |
download | linux-stable-9eab9901b015f489199105c470de1ffc337cfabb.tar.gz linux-stable-9eab9901b015f489199105c470de1ffc337cfabb.tar.bz2 linux-stable-9eab9901b015f489199105c470de1ffc337cfabb.zip |
powerpc/powernv: Fix concurrency issue with npu->mmio_atsd_usage
We've encountered a performance issue when multiple processors stress
{get,put}_mmio_atsd_reg(). These functions contend for
mmio_atsd_usage, an unsigned long used as a bitmask.
The accesses to mmio_atsd_usage are done using test_and_set_bit_lock()
and clear_bit_unlock(). As implemented, both of these will require
a (successful) stwcx to that same cache line.
What we end up with is thread A, attempting to unlock, being slowed by
other threads repeatedly attempting to lock. A's stwcx instructions
fail and retry because the memory reservation is lost every time a
different thread beats it to the punch.
There may be a long-term way to fix this at a larger scale, but for
now resolve the immediate problem by gating our call to
test_and_set_bit_lock() with one to test_bit(), which is obviously
implemented without using a store.
Fixes: 1ab66d1fbada ("powerpc/powernv: Introduce address translation services for Nvlink2")
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Acked-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/tools/checkpatch.sh')
0 files changed, 0 insertions, 0 deletions