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| author | Charlie Jenkins <charlie@rivosinc.com> | 2024-03-12 16:53:41 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-04-18 08:10:58 -0700 |
| commit | 6b9391b581fddd8579239dad4de4f0393149e10a (patch) | |
| tree | cc60083c637b481c0df1f5e8e426b05cf25b0534 /arch/riscv/include/asm/mmu.h | |
| parent | bebc345413f5fb4c8fafb59ff0bd8509197627e6 (diff) | |
| download | linux-stable-6b9391b581fddd8579239dad4de4f0393149e10a.tar.gz linux-stable-6b9391b581fddd8579239dad4de4f0393149e10a.tar.bz2 linux-stable-6b9391b581fddd8579239dad4de4f0393149e10a.zip | |
riscv: Include riscv_set_icache_flush_ctx prctl
Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable
optimization of cross modifying code. This prctl enables userspace code
to use icache flushing instructions such as fence.i with the guarantee
that the icache will continue to be clean after thread migration.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20240312-fencei-v13-2-4b6bdc2bbf32@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/mmu.h')
| -rw-r--r-- | arch/riscv/include/asm/mmu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 355504b37f8e..60be458e94da 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -19,6 +19,8 @@ typedef struct { #ifdef CONFIG_SMP /* A local icache flush is needed before user execution can resume. */ cpumask_t icache_stale_mask; + /* Force local icache flush on all migrations. */ + bool force_icache_flush; #endif #ifdef CONFIG_BINFMT_ELF_FDPIC unsigned long exec_fdpic_loadmap; |