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| author | Evan Green <evan@rivosinc.com> | 2023-05-09 11:25:03 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-19 09:53:10 -0700 |
| commit | c0baf321038d5fa4273c0dc495d78f39848dd8fc (patch) | |
| tree | 27ac91fb3521ca72078e3d0d5b908772dd0ebd29 /arch/riscv/include/uapi/asm/hwprobe.h | |
| parent | 82e9c66e81c814e20ee2a3aafb60a9012c79fb40 (diff) | |
| download | linux-stable-c0baf321038d5fa4273c0dc495d78f39848dd8fc.tar.gz linux-stable-c0baf321038d5fa4273c0dc495d78f39848dd8fc.tar.bz2 linux-stable-c0baf321038d5fa4273c0dc495d78f39848dd8fc.zip | |
RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions.
These are accurately reported per CPU.
Signed-off-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20230509182504.2997252-4-evan@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/uapi/asm/hwprobe.h')
| -rw-r--r-- | arch/riscv/include/uapi/asm/hwprobe.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 8d745a4ad8a2..853f8f6d9a42 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,9 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) +#define RISCV_HWPROBE_EXT_ZBS (1 << 4) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) |