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authorClément Léger <cleger@rivosinc.com>2023-11-14 09:12:46 -0500
committerPalmer Dabbelt <palmer@rivosinc.com>2023-12-12 15:45:07 -0800
commitbf4cd84111c6139313504310ff934df901a5ed3e (patch)
tree7d069106704df819a66fc9bd827b61e8dc77af36 /arch/riscv/include/uapi/asm
parent11e8e1ee2c223585f1776e5c5d21bdae7184ca34 (diff)
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riscv: hwprobe: export Zfh[min] ISA extensions
Export Zfh[min] ISA extensions[1] through hwprobe only if FPU support is available. Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1] Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Evan Green <evan@rivosinc.com> Link: https://lore.kernel.org/r/20231114141256.126749-11-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/uapi/asm')
-rw-r--r--arch/riscv/include/uapi/asm/hwprobe.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 89628a76ca04..2d960777ea43 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -50,6 +50,8 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24)
#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25)
#define RISCV_HWPROBE_EXT_ZVKT (1 << 26)
+#define RISCV_HWPROBE_EXT_ZFH (1 << 27)
+#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)