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| author | Anup Patel <apatel@ventanamicro.com> | 2022-05-09 10:43:39 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-05-20 09:09:04 +0530 |
| commit | b4bbb95ea6c41a616385902df81a66293f4b744c (patch) | |
| tree | c9d418c9a33ea8c27db1e8155501ccb3b1236148 /arch/riscv/include | |
| parent | 26708234eb12e73a2a475296f562ba351fb39894 (diff) | |
| download | linux-stable-b4bbb95ea6c41a616385902df81a66293f4b744c.tar.gz linux-stable-b4bbb95ea6c41a616385902df81a66293f4b744c.tar.bz2 linux-stable-b4bbb95ea6c41a616385902df81a66293f4b744c.zip | |
RISC-V: KVM: Add Sv57x4 mode support for G-stage
Latest QEMU supports G-stage Sv57x4 mode so this patch extends KVM
RISC-V G-stage handling to detect and use Sv57x4 mode when available.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index e935f27b10fd..cc40521e438b 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -117,6 +117,7 @@ #define HGATP_MODE_SV32X4 _AC(1, UL) #define HGATP_MODE_SV39X4 _AC(8, UL) #define HGATP_MODE_SV48X4 _AC(9, UL) +#define HGATP_MODE_SV57X4 _AC(10, UL) #define HGATP32_MODE_SHIFT 31 #define HGATP32_VMID_SHIFT 22 |