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| author | Jisheng Zhang <jszhang@kernel.org> | 2021-11-18 19:26:05 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-01-05 17:52:54 -0800 |
| commit | 2bf847db0c7437c28b10fba2981b9a7db4b4e0e2 (patch) | |
| tree | f0248762ab49f86e123c5ac25f457e3565677d2b /arch/riscv/kernel/vmlinux.lds.S | |
| parent | 6dd10d9166a0c06260e0ac6b1fac454117c8024a (diff) | |
| download | linux-stable-2bf847db0c7437c28b10fba2981b9a7db4b4e0e2.tar.gz linux-stable-2bf847db0c7437c28b10fba2981b9a7db4b4e0e2.tar.bz2 linux-stable-2bf847db0c7437c28b10fba2981b9a7db4b4e0e2.zip | |
riscv: extable: add `type` and `data` fields
This is a riscv port of commit d6e2cc564775 ("arm64: extable: add `type`
and `data` fields").
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/kernel/vmlinux.lds.S')
| -rw-r--r-- | arch/riscv/kernel/vmlinux.lds.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S index 5104f3a871e3..0e5ae851929e 100644 --- a/arch/riscv/kernel/vmlinux.lds.S +++ b/arch/riscv/kernel/vmlinux.lds.S @@ -4,7 +4,7 @@ * Copyright (C) 2017 SiFive */ -#define RO_EXCEPTION_TABLE_ALIGN 16 +#define RO_EXCEPTION_TABLE_ALIGN 4 #ifdef CONFIG_XIP_KERNEL #include "vmlinux-xip.lds.S" |