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author | Samuel Holland <samuel.holland@sifive.com> | 2024-03-12 12:56:38 -0700 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-04-28 14:50:36 -0700 |
commit | fa7d7339016ab7850258e85d6adfd4c4abca5498 (patch) | |
tree | 9d3fa584dbbcfc361df629bffeaffee04969e2f4 /arch/riscv/kernel | |
parent | d4b500cceb0e09ae22722d41454df6012848062b (diff) | |
download | linux-stable-fa7d7339016ab7850258e85d6adfd4c4abca5498.tar.gz linux-stable-fa7d7339016ab7850258e85d6adfd4c4abca5498.tar.bz2 linux-stable-fa7d7339016ab7850258e85d6adfd4c4abca5498.zip |
riscv: Do not save the scratch CSR during suspend
While the processor is executing kernel code, the value of the scratch
CSR is always zero, so there is no need to save the value. Continue to
write the CSR during the resume flow, so we do not rely on firmware to
initialize it.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20240312195641.1830521-1-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/kernel')
-rw-r--r-- | arch/riscv/kernel/suspend.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 8a327b485b90..c8cec0cc5833 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -14,7 +14,6 @@ void suspend_save_csrs(struct suspend_context *context) { - context->scratch = csr_read(CSR_SCRATCH); if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) context->envcfg = csr_read(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { - csr_write(CSR_SCRATCH, context->scratch); + csr_write(CSR_SCRATCH, 0); if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); |