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| author | Anup Patel <apatel@ventanamicro.com> | 2023-09-15 17:51:10 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-10-12 18:44:23 +0530 |
| commit | df68f4d8cb496ea31fa42cf2620366571c05376b (patch) | |
| tree | 01a906d60f0518835fc246ce8d1aa88275df4d3b /arch/riscv/kvm | |
| parent | 6a53a5fbc8f494e69922e13491f7077ce010ec28 (diff) | |
| download | linux-stable-df68f4d8cb496ea31fa42cf2620366571c05376b.tar.gz linux-stable-df68f4d8cb496ea31fa42cf2620366571c05376b.tar.bz2 linux-stable-df68f4d8cb496ea31fa42cf2620366571c05376b.zip | |
RISC-V: KVM: Allow Zicond extension for Guest/VM
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zicond extension for Guest/VM.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm')
| -rw-r--r-- | arch/riscv/kvm/vcpu_onereg.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 388599fcf684..c6ebce6126b5 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -46,6 +46,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZICBOM), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), KVM_ISA_EXT_ARR(ZIFENCEI), KVM_ISA_EXT_ARR(ZIHINTPAUSE), @@ -93,6 +94,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZBB: case KVM_RISCV_ISA_EXT_ZBS: case KVM_RISCV_ISA_EXT_ZICNTR: + case KVM_RISCV_ISA_EXT_ZICOND: case KVM_RISCV_ISA_EXT_ZICSR: case KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: |