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author | Jisheng Zhang <jszhang@kernel.org> | 2021-11-18 19:22:51 +0800 |
---|---|---|
committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-01-05 17:52:20 -0800 |
commit | bb1f85d6046f0db757ac52ed60a5eba5df394819 (patch) | |
tree | 0f08ecba35bbe486c8e0130153f143a567cfb936 /arch/riscv/lib/uaccess.S | |
parent | f8f2ad02ee438b7dbceaac947077eaf77c823646 (diff) | |
download | linux-stable-bb1f85d6046f0db757ac52ed60a5eba5df394819.tar.gz linux-stable-bb1f85d6046f0db757ac52ed60a5eba5df394819.tar.bz2 linux-stable-bb1f85d6046f0db757ac52ed60a5eba5df394819.zip |
riscv: switch to relative exception tables
Similar as other architectures such as arm64, x86 and so on, use
offsets relative to the exception table entry values rather than
absolute addresses for both the exception locationand the fixup.
However, RISCV label difference will actually produce two relocations,
a pair of R_RISCV_ADD32 and R_RISCV_SUB32. Take below simple code for
example:
$ cat test.S
.section .text
1:
nop
.section __ex_table,"a"
.balign 4
.long (1b - .)
.previous
$ riscv64-linux-gnu-gcc -c test.S
$ riscv64-linux-gnu-readelf -r test.o
Relocation section '.rela__ex_table' at offset 0x100 contains 2 entries:
Offset Info Type Sym. Value Sym. Name + Addend
000000000000 000600000023 R_RISCV_ADD32 0000000000000000 .L1^B1 + 0
000000000000 000500000027 R_RISCV_SUB32 0000000000000000 .L0 + 0
The modpost will complain the R_RISCV_SUB32 relocation, so we need to
patch modpost.c to skip this relocation for .rela__ex_table section.
After this patch, the __ex_table section size of defconfig vmlinux is
reduced from 7072 Bytes to 3536 Bytes.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/lib/uaccess.S')
-rw-r--r-- | arch/riscv/lib/uaccess.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index 63bc691cff91..55f80f84e23f 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -7,8 +7,8 @@ 100: \op \reg, \addr .section __ex_table,"a" - .balign RISCV_SZPTR - RISCV_PTR 100b, \lbl + .balign 4 + .long (100b - .), (\lbl - .) .previous .endm |