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authorConor Dooley <conor.dooley@microchip.com>2022-05-09 15:26:10 +0100
committerPalmer Dabbelt <palmer@rivosinc.com>2022-06-01 15:28:40 -0700
commit1bcea0303ff32d0d1671226d77dc837eef1a93c9 (patch)
treeca94d3c62cf4045474e6837d655f91e121e336f0 /arch/riscv
parentbc47b2217f246ed0bf0305dd7572f76fc8a3b85c (diff)
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riscv: microchip: icicle: readability fixes
Fix the sort order of the status properties, remove some extra whitespace in the mmc entry & add whitespace to the mac entry containing the phys so that the dt is easier to read. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20220509142610.128590-10-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 739dfa52bed1..9cd1a30edf2c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -64,8 +64,6 @@
};
&mmc {
- status = "okay";
-
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
@@ -77,6 +75,7 @@
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
+ status = "okay";
};
&spi0 {
@@ -106,16 +105,19 @@
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
+ status = "okay";
};
&mac1 {
- status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
+ status = "okay";
+
phy1: ethernet-phy@9 {
reg = <9>;
ti,fifo-depth = <0x1>;
};
+
phy0: ethernet-phy@8 {
reg = <8>;
ti,fifo-depth = <0x1>;