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| author | John Watts <contact@jookia.org> | 2023-07-22 08:15:51 +1000 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2023-07-28 08:47:18 +0200 |
| commit | 6ea1ad888f5900953a21853e709fa499fdfcb317 (patch) | |
| tree | 3760dc33f1d93c5b0e2e2f70dd95c0804402e5b8 /arch/riscv | |
| parent | 8c07fb0d647772018e0562fc4e920e081efb4c80 (diff) | |
| download | linux-stable-6ea1ad888f5900953a21853e709fa499fdfcb317.tar.gz linux-stable-6ea1ad888f5900953a21853e709fa499fdfcb317.tar.bz2 linux-stable-6ea1ad888f5900953a21853e709fa499fdfcb317.zip | |
riscv: dts: allwinner: d1: Add CAN controller nodes
The Allwinner D1, T113 provide two CAN controllers that are variants
of the R40 controller.
I have tested support for these controllers on two boards:
- A Lichee Panel RV 86 Panel running a D1 chip
- A Mango Pi MQ Dual running a T113-s3 chip
Both of these fully support both CAN controllers.
Signed-off-by: John Watts <contact@jookia.org>
Link: https://lore.kernel.org/all/20230721221552.1973203-4-contact@jookia.org
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 1bb1e5cae602..4086c0cc0f9d 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -131,6 +131,18 @@ pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + can0_pins: can0-pins { + pins = "PB2", "PB3"; + function = "can0"; + }; + + /omit-if-no-ref/ + can1_pins: can1-pins { + pins = "PB4", "PB5"; + function = "can1"; + }; }; ccu: clock-controller@2001000 { @@ -879,5 +891,23 @@ clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + can0: can@2504000 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504000 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN0>; + resets = <&ccu RST_BUS_CAN0>; + status = "disabled"; + }; + + can1: can@2504400 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504400 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN1>; + resets = <&ccu RST_BUS_CAN1>; + status = "disabled"; + }; }; }; |