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| author | Atish Patra <atishp@rivosinc.com> | 2024-04-20 08:17:17 -0700 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-04-22 11:13:42 +0530 |
| commit | d1927f64e0e1094f296842e127138cb5f3bf3c6d (patch) | |
| tree | 26808337043ea2c0cbebc2238f1353533eaa26f7 /arch/riscv | |
| parent | 9752fed8f67c258213535d72f7669279921a6491 (diff) | |
| download | linux-stable-d1927f64e0e1094f296842e127138cb5f3bf3c6d.tar.gz linux-stable-d1927f64e0e1094f296842e127138cb5f3bf3c6d.tar.bz2 linux-stable-d1927f64e0e1094f296842e127138cb5f3bf3c6d.zip | |
RISC-V: Fix the typo in Scountovf CSR name
The counter overflow CSR name is "scountovf" not "sscountovf".
Fix the csr name.
Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240420151741.962500-2-atishp@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..9d1b07932794 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 |