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| author | Like Xu <likexu@tencent.com> | 2022-09-19 17:10:08 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-11-09 12:26:54 -0500 |
| commit | 556f3c9ad7c101aa16a43ef4539f3aabc1d7b32e (patch) | |
| tree | 85f71e58ad57f76644835d480629686531e8a4f9 /arch/x86/events/rapl.c | |
| parent | 4f1fa2a1bbeb2feca436d2c86bf6f78dc4e5e4c4 (diff) | |
| download | linux-stable-556f3c9ad7c101aa16a43ef4539f3aabc1d7b32e.tar.gz linux-stable-556f3c9ad7c101aa16a43ef4539f3aabc1d7b32e.tar.bz2 linux-stable-556f3c9ad7c101aa16a43ef4539f3aabc1d7b32e.zip | |
KVM: x86/pmu: Limit the maximum number of supported AMD GP counters
The AMD PerfMonV2 specification allows for a maximum of 16 GP counters,
but currently only 6 pairs of MSRs are accepted by KVM.
While AMD64_NUM_COUNTERS_CORE is already equal to 6, increasing without
adjusting msrs_to_save_all[] could result in out-of-bounds accesses.
Therefore introduce a macro (named KVM_AMD_PMC_MAX_GENERIC) to
refer to the number of counters supported by KVM.
Signed-off-by: Like Xu <likexu@tencent.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Message-Id: <20220919091008.60695-3-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/events/rapl.c')
0 files changed, 0 insertions, 0 deletions