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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2018-05-17 17:09:18 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-05-17 17:09:18 +0200 |
| commit | 11fb0683493b2da112cd64c9dada221b52463bf7 (patch) | |
| tree | 4a1b5caae3b4e322b31d6c7ee4f9c4d6fdd870cb /arch/x86/events | |
| parent | ccbcd2674472a978b48c91c1fbfb66c0ff959f24 (diff) | |
| download | linux-stable-11fb0683493b2da112cd64c9dada221b52463bf7.tar.gz linux-stable-11fb0683493b2da112cd64c9dada221b52463bf7.tar.bz2 linux-stable-11fb0683493b2da112cd64c9dada221b52463bf7.zip | |
x86/speculation: Add virtualized speculative store bypass disable support
Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.
Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'arch/x86/events')
0 files changed, 0 insertions, 0 deletions