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| author | Wei Wang <wei.w.wang@intel.com> | 2020-06-13 16:09:46 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-07-02 15:51:45 +0200 |
| commit | 3cb9d5464c1ceea86f6225089b2f7965989cf316 (patch) | |
| tree | 4c587f3a7517e98040de123521f8bcf6bd34e281 /arch/x86/events | |
| parent | 9ebcfadb0610322ac537dd7aa5d9cbc2b2894c68 (diff) | |
| download | linux-stable-3cb9d5464c1ceea86f6225089b2f7965989cf316.tar.gz linux-stable-3cb9d5464c1ceea86f6225089b2f7965989cf316.tar.bz2 linux-stable-3cb9d5464c1ceea86f6225089b2f7965989cf316.zip | |
perf/x86: Fix variable types for LBR registers
The MSR variable type can be 'unsigned int', which uses less memory than
the longer 'unsigned long'. Fix 'struct x86_pmu' for that. The lbr_nr won't
be a negative number, so make it 'unsigned int' as well.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200613080958.132489-2-like.xu@linux.intel.com
Diffstat (limited to 'arch/x86/events')
| -rw-r--r-- | arch/x86/events/perf_event.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index e17a3d8a47ed..eb37f6c43c96 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -673,8 +673,8 @@ struct x86_pmu { /* * Intel LBR */ - unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ - int lbr_nr; /* hardware stack size */ + unsigned int lbr_tos, lbr_from, lbr_to, + lbr_nr; /* LBR base regs and size */ u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */ |