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| author | Thomas Gleixner <tglx@linutronix.de> | 2020-08-26 13:16:33 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2020-09-16 16:52:28 +0200 |
| commit | b0a19555efd098183db0ee3ad52a3cd3bfbd1ba2 (patch) | |
| tree | 653c56015c1c89a6128e6483b938bf8fb73e1c30 /arch/x86/include/asm/apic.h | |
| parent | 13b90cadfc294718dd5a89e1fcf103477b01eb50 (diff) | |
| download | linux-stable-b0a19555efd098183db0ee3ad52a3cd3bfbd1ba2.tar.gz linux-stable-b0a19555efd098183db0ee3ad52a3cd3bfbd1ba2.tar.bz2 linux-stable-b0a19555efd098183db0ee3ad52a3cd3bfbd1ba2.zip | |
x86/msi: Move compose message callback where it belongs
Composing the MSI message at the MSI chip level is wrong because the
underlying parent domain is the one which knows how the message should be
composed for the direct vector delivery or the interrupt remapping table
entry.
The interrupt remapping aware PCI/MSI chip does that already. Make the
direct delivery chip do the same and move the composition of the direct
delivery MSI message to the vector domain irq chip.
This prepares for the upcoming device MSI support to avoid having
architecture specific knowledge in the device MSI domain irq chips.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20200826112331.157603198@linutronix.de
Diffstat (limited to 'arch/x86/include/asm/apic.h')
| -rw-r--r-- | arch/x86/include/asm/apic.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 2cc44e957c31..1c129abb7f09 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -519,6 +519,14 @@ static inline bool apic_id_is_primary_thread(unsigned int id) { return false; } static inline void apic_smt_update(void) { } #endif +struct msi_msg; + +#ifdef CONFIG_PCI_MSI +void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg); +#else +# define x86_vector_msi_compose_msg NULL +#endif + extern void ioapic_zap_locks(void); #endif /* _ASM_X86_APIC_H */ |