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| author | Kim Phillips <kim.phillips@amd.com> | 2023-01-24 10:33:16 -0600 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2023-01-25 16:25:46 +0100 |
| commit | 5b909d4ae59aedc711b7a432da021be0e82c95a0 (patch) | |
| tree | 6058d658298f09fd039686e827fe510010692021 /arch/x86/include/asm/cpufeatures.h | |
| parent | 84168ae786f8a15a7eb0f79d34f20b8d261ce2f5 (diff) | |
| download | linux-stable-5b909d4ae59aedc711b7a432da021be0e82c95a0.tar.gz linux-stable-5b909d4ae59aedc711b7a432da021be0e82c95a0.tar.bz2 linux-stable-5b909d4ae59aedc711b7a432da021be0e82c95a0.zip | |
x86/cpu, kvm: Add the Null Selector Clears Base feature
The Null Selector Clears Base feature was being open-coded for KVM.
Add it to its newly added native CPUID leaf 0x80000021 EAX proper.
Also drop the bit description comments now it's more self-describing.
[ bp: Convert test in check_null_seg_clears_base() too. ]
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20230124163319.2277355-6-kim.phillips@amd.com
Diffstat (limited to 'arch/x86/include/asm/cpufeatures.h')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 901128ed4c7a..6bed80cf0dc5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -430,6 +430,7 @@ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ +#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */ /* * BUG word(s) |