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| author | Thomas Gleixner <tglx@linutronix.de> | 2022-09-15 13:11:19 +0200 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-10-17 16:41:11 +0200 |
| commit | 80e4c1cd42fff110bfdae8fce7ac4f22465f9664 (patch) | |
| tree | 72eb9d2152e2c6af9f82d92c4508302b0d044fe8 /arch/x86/include/asm/cpufeatures.h | |
| parent | bea75b33895f7f87f0c40023e36a2d087e87ffa1 (diff) | |
| download | linux-stable-80e4c1cd42fff110bfdae8fce7ac4f22465f9664.tar.gz linux-stable-80e4c1cd42fff110bfdae8fce7ac4f22465f9664.tar.bz2 linux-stable-80e4c1cd42fff110bfdae8fce7ac4f22465f9664.zip | |
x86/retbleed: Add X86_FEATURE_CALL_DEPTH
Intel SKL CPUs fall back to other predictors when the RSB underflows. The
only microcode mitigation is IBRS which is insanely expensive. It comes
with performance drops of up to 30% depending on the workload.
A way less expensive, but nevertheless horrible mitigation is to track the
call depth in software and overeagerly fill the RSB when returns underflow
the software counter.
Provide a configuration symbol and a CPU misfeature bit.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220915111147.056176424@infradead.org
Diffstat (limited to 'arch/x86/include/asm/cpufeatures.h')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b71f4f2ecdd5..aefd0816a333 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -304,6 +304,7 @@ #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ +#define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth tracking for RSB stuffing */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ |