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| author | Stephane Eranian <eranian@google.com> | 2022-03-22 15:15:06 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-04-05 10:24:36 +0200 |
| commit | a77d41ac3a0f41c80120ec5b8b08ab284fec950a (patch) | |
| tree | 229ce1025c8c99806ecd2a0405dde2a41d1967ad /arch/x86/include/asm/cpufeatures.h | |
| parent | bfe4daf850f45d92dcd3da477f0b0456620294c3 (diff) | |
| download | linux-stable-a77d41ac3a0f41c80120ec5b8b08ab284fec950a.tar.gz linux-stable-a77d41ac3a0f41c80120ec5b8b08ab284fec950a.tar.bz2 linux-stable-a77d41ac3a0f41c80120ec5b8b08ab284fec950a.zip | |
x86/cpufeatures: Add AMD Fam19h Branch Sampling feature
Add a cpu feature for AMD Fam19h Branch Sampling feature as bit
31 of EBX on CPUID leaf function 0x80000008.
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220322221517.2510440-3-eranian@google.com
Diffstat (limited to 'arch/x86/include/asm/cpufeatures.h')
| -rw-r--r-- | arch/x86/include/asm/cpufeatures.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 73e643ae94b6..0d62afd525e3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -315,6 +315,7 @@ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ +#define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ |