diff options
author | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2018-05-16 23:18:09 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2018-05-18 11:17:30 +0200 |
commit | 240da953fcc6a9008c92fae5b1f727ee5ed167ab (patch) | |
tree | 7d2220f310b3a8a4a03ecc6c5b39a6571ad3280e /arch/x86/include/asm/msr-index.h | |
parent | bc226f07dcd3c9ef0b7f6236fe356ea4a9cb4769 (diff) | |
download | linux-stable-240da953fcc6a9008c92fae5b1f727ee5ed167ab.tar.gz linux-stable-240da953fcc6a9008c92fae5b1f727ee5ed167ab.tar.bz2 linux-stable-240da953fcc6a9008c92fae5b1f727ee5ed167ab.zip |
x86/bugs: Rename SSBD_NO to SSB_NO
The "336996 Speculative Execution Side Channel Mitigations" from
May defines this as SSB_NO, hence lets sync-up.
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
-rw-r--r-- | arch/x86/include/asm/msr-index.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 562414d5b834..fda2114197b3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -70,7 +70,7 @@ #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ -#define ARCH_CAP_SSBD_NO (1 << 4) /* +#define ARCH_CAP_SSB_NO (1 << 4) /* * Not susceptible to Speculative Store Bypass * attack, so no Speculative Store Bypass * control required. |