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| author | Chao Peng <chao.p.peng@linux.intel.com> | 2018-10-24 16:05:10 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2018-12-21 11:28:34 +0100 |
| commit | f99e3daf94ff35dd4a878d32ff66e1fd35223ad6 (patch) | |
| tree | 979e4d97a69fe57456981d297c7c102392fdae2f /arch/x86/include/asm/msr-index.h | |
| parent | e0018afec50a4846789d92a1b7cd6cd7f816c448 (diff) | |
| download | linux-stable-f99e3daf94ff35dd4a878d32ff66e1fd35223ad6.tar.gz linux-stable-f99e3daf94ff35dd4a878d32ff66e1fd35223ad6.tar.bz2 linux-stable-f99e3daf94ff35dd4a878d32ff66e1fd35223ad6.zip | |
KVM: x86: Add Intel PT virtualization work mode
Intel Processor Trace virtualization can be work in one
of 2 possible modes:
a. System-Wide mode (default):
When the host configures Intel PT to collect trace packets
of the entire system, it can leave the relevant VMX controls
clear to allow VMX-specific packets to provide information
across VMX transitions.
KVM guest will not aware this feature in this mode and both
host and KVM guest trace will output to host buffer.
b. Host-Guest mode:
Host can configure trace-packet generation while in
VMX non-root operation for guests and root operation
for native executing normally.
Intel PT will be exposed to KVM guest in this mode, and
the trace output to respective buffer of host and guest.
In this mode, tht status of PT will be saved and disabled
before VM-entry and restored after VM-exit if trace
a virtual machine.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6a900150184b..8f95297371af 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -807,6 +807,7 @@ #define VMX_BASIC_INOUT 0x0040000000000000LLU /* MSR_IA32_VMX_MISC bits */ +#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F /* AMD-V MSRs */ |