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authorHans Rosenfeld <hans.rosenfeld@amd.com>2011-01-24 16:05:41 +0100
committerIngo Molnar <mingo@elte.hu>2011-01-26 08:28:23 +0100
commitb453de02b786c63b8928ec822401468131db0a9b (patch)
tree9cb66105460f44a4a425418de268204da7807578 /arch/x86/kernel/amd_nb.c
parentd518573de63fb119e5e9a3137386544671387681 (diff)
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x86, amd: Enable L3 cache index disable on family 0x15
AMD family 0x15 CPUs support L3 cache index disable, so enable it on them. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Cc: <andreas.herrmann3@amd.com> LKML-Reference: <1295881543-572552-3-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/amd_nb.c')
-rw-r--r--arch/x86/kernel/amd_nb.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 0a99f7198bc3..a4f394c8e055 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -85,6 +85,9 @@ int amd_cache_northbridges(void)
boot_cpu_data.x86_mask >= 0x1))
amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
+ if (boot_cpu_data.x86 == 0x15)
+ amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
+
return 0;
}
EXPORT_SYMBOL_GPL(amd_cache_northbridges);