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author | Borislav Petkov <bp@suse.de> | 2021-05-10 23:29:25 +0200 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2021-05-18 14:49:21 +0200 |
commit | b1efd0ff4bd16e8bb8607ba566b03f2024a830bb (patch) | |
tree | 3432711b593241ed271680a0b624b34c7f291395 /arch/x86/kernel/traps.c | |
parent | d07f6ca923ea0927a1024dfccafc5b53b61cfecc (diff) | |
download | linux-stable-b1efd0ff4bd16e8bb8607ba566b03f2024a830bb.tar.gz linux-stable-b1efd0ff4bd16e8bb8607ba566b03f2024a830bb.tar.bz2 linux-stable-b1efd0ff4bd16e8bb8607ba566b03f2024a830bb.zip |
x86/cpu: Init AP exception handling from cpu_init_secondary()
SEV-ES guests require properly setup task register with which the TSS
descriptor in the GDT can be located so that the IST-type #VC exception
handler which they need to function properly, can be executed.
This setup needs to happen before attempting to load microcode in
ucode_cpu_init() on secondary CPUs which can cause such #VC exceptions.
Simplify the machinery by running that exception setup from a new function
cpu_init_secondary() and explicitly call cpu_init_exception_handling() for
the boot CPU before cpu_init(). The latter prepares for fixing and
simplifying the exception/IST setup on the boot CPU.
There should be no functional changes resulting from this patch.
[ tglx: Reworked it so cpu_init_exception_handling() stays seperate ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Lai Jiangshan <laijs@linux.alibaba.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/87k0o6gtvu.ffs@nanos.tec.linutronix.de
Diffstat (limited to 'arch/x86/kernel/traps.c')
-rw-r--r-- | arch/x86/kernel/traps.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 853ea7a80806..41f7dc492803 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -1162,9 +1162,7 @@ void __init trap_init(void) idt_setup_traps(); - /* - * Should be a barrier for any external CPU state: - */ + cpu_init_exception_handling(); cpu_init(); idt_setup_ist_traps(); |