summaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
authorConor Dooley <conor.dooley@microchip.com>2023-06-07 21:28:27 +0100
committerPalmer Dabbelt <palmer@rivosinc.com>2023-06-21 07:45:15 -0700
commit069b0d51707721d5ab2001df866b66b82e4c1c35 (patch)
tree90a1f48a467c858ce8b0ba66d469efa3c8f5773f /arch
parent2ac874343749b76e069cff5fea09c49e0bd365a0 (diff)
downloadlinux-stable-069b0d51707721d5ab2001df866b66b82e4c1c35.tar.gz
linux-stable-069b0d51707721d5ab2001df866b66b82e4c1c35.tar.bz2
linux-stable-069b0d51707721d5ab2001df866b66b82e4c1c35.zip
RISC-V: validate riscv,isa at boot, not during ISA string parsing
Since riscv_fill_hwcap() now only iterates over possible cpus, the basic validation of whether riscv,isa contains "rv<width>" can be moved to riscv_early_of_processor_hartid(). Further, "ima" support is required by the kernel, so reject any CPU not fitting the bill. Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Link: https://lore.kernel.org/r/20230607-guts-blurry-67e711acf328@spud Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/kernel/cpu.c8
-rw-r--r--arch/riscv/kernel/cpufeature.c12
2 files changed, 11 insertions, 9 deletions
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 8025de06edb7..dfb4a2a61050 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -65,10 +65,12 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
return -ENODEV;
}
- if (tolower(isa[0]) != 'r' || tolower(isa[1]) != 'v') {
- pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
+
+ if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7))
+ return -ENODEV;
+
+ if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7))
return -ENODEV;
- }
return 0;
}
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c8635211fc18..c3851c8cfa9c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -148,12 +148,12 @@ void __init riscv_fill_hwcap(void)
}
}
- if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4))
- continue;
-
- if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4))
- continue;
-
+ /*
+ * For all possible cpus, we have already validated in
+ * the boot process that they at least contain "rv" and
+ * whichever of "32"/"64" this kernel supports, and so this
+ * section can be skipped.
+ */
isa += 4;
bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);