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| author | Nishanth Menon <nm@ti.com> | 2023-06-06 13:22:17 -0500 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2023-06-15 11:05:48 +0530 |
| commit | 0e97d245633bffc0ae348c95f98a2af5b973811c (patch) | |
| tree | ea1599428711dee3c61cadad14f8e5a0b2989869 /arch | |
| parent | bb867df51d3b7f305222405c4e01373efc8866c7 (diff) | |
| download | linux-stable-0e97d245633bffc0ae348c95f98a2af5b973811c.tar.gz linux-stable-0e97d245633bffc0ae348c95f98a2af5b973811c.tar.bz2 linux-stable-0e97d245633bffc0ae348c95f98a2af5b973811c.zip | |
arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-12-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am642-sk.dts | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 9ea012b883e8..3e27bd65cb2e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -480,8 +480,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default - &rgmii2_pins_default>; + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { @@ -613,25 +612,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; |