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| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-03-16 15:12:58 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-04-04 20:18:31 -0700 |
| commit | 2f51d9231485250c0e4cf4d7326c30109c553382 (patch) | |
| tree | af241cc314bafb84475befe4e33446ff147a04bc /arch | |
| parent | 31cc61104f6894f686491dbbb5c8ece97b06e75d (diff) | |
| download | linux-stable-2f51d9231485250c0e4cf4d7326c30109c553382.tar.gz linux-stable-2f51d9231485250c0e4cf4d7326c30109c553382.tar.bz2 linux-stable-2f51d9231485250c0e4cf4d7326c30109c553382.zip | |
arm64: dts: qcom: sm6375: Add CPUCP L3 node
Configure the L3 cache DVFS scaler within the CPUCP block to allow
for dynamic frequency switching.
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-9-708b8191f7eb@linaro.org
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index b768b767604f..a5dde682ede0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1513,6 +1513,15 @@ }; }; + cpucp_l3: interconnect@fd90000 { + compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; + reg = <0 0x0fd90000 0 0x1000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@fd91000 { compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; |