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author | Paul Mundt <lethal@linux-sh.org> | 2008-07-29 22:52:49 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-29 22:52:49 +0900 |
commit | 51f3547d619956e9b428bfff17004d8f4d259a02 (patch) | |
tree | 8e035f60124ece835a9acb3cf84dc2af887cefc3 /arch | |
parent | 93dc544cf4892b9188d7d0d4946b0394020b4551 (diff) | |
download | linux-stable-51f3547d619956e9b428bfff17004d8f4d259a02.tar.gz linux-stable-51f3547d619956e9b428bfff17004d8f4d259a02.tar.bz2 linux-stable-51f3547d619956e9b428bfff17004d8f4d259a02.zip |
sh: Allow SH-3 and SH-5 to use common headers.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/sh/include/cpu-common/cpu/rtc.h (renamed from arch/sh/include/cpu-sh2/cpu/rtc.h) | 0 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh3/cpu/addrspace.h | 19 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh3/cpu/cacheflush.h | 36 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh3/cpu/rtc.h | 8 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh3/cpu/sigcontext.h | 17 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh5/cpu/timer.h | 4 |
6 files changed, 1 insertions, 83 deletions
diff --git a/arch/sh/include/cpu-sh2/cpu/rtc.h b/arch/sh/include/cpu-common/cpu/rtc.h index 39e2d6e94782..39e2d6e94782 100644 --- a/arch/sh/include/cpu-sh2/cpu/rtc.h +++ b/arch/sh/include/cpu-common/cpu/rtc.h diff --git a/arch/sh/include/cpu-sh3/cpu/addrspace.h b/arch/sh/include/cpu-sh3/cpu/addrspace.h deleted file mode 100644 index 0f94726c7d62..000000000000 --- a/arch/sh/include/cpu-sh3/cpu/addrspace.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Kaz Kojima - * - * Defitions for the address spaces of the SH-3 CPUs. - */ -#ifndef __ASM_CPU_SH3_ADDRSPACE_H -#define __ASM_CPU_SH3_ADDRSPACE_H - -#define P0SEG 0x00000000 -#define P1SEG 0x80000000 -#define P2SEG 0xa0000000 -#define P3SEG 0xc0000000 -#define P4SEG 0xe0000000 - -#endif /* __ASM_CPU_SH3_ADDRSPACE_H */ diff --git a/arch/sh/include/cpu-sh3/cpu/cacheflush.h b/arch/sh/include/cpu-sh3/cpu/cacheflush.h index f70d8ef76a15..abc909880807 100644 --- a/arch/sh/include/cpu-sh3/cpu/cacheflush.h +++ b/arch/sh/include/cpu-sh3/cpu/cacheflush.h @@ -10,25 +10,7 @@ #ifndef __ASM_CPU_SH3_CACHEFLUSH_H #define __ASM_CPU_SH3_CACHEFLUSH_H -/* - * Cache flushing: - * - * - flush_cache_all() flushes entire cache - * - flush_cache_mm(mm) flushes the specified mm context's cache lines - * - flush_cache_dup mm(mm) handles cache flushing when forking - * - flush_cache_page(mm, vmaddr, pfn) flushes a single page - * - flush_cache_range(vma, start, end) flushes a range of pages - * - * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache - * - flush_icache_range(start, end) flushes(invalidates) a range for icache - * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache - * - * Caches are indexed (effectively) by physical address on SH-3, so - * we don't need them. - */ - #if defined(CONFIG_SH7705_CACHE_32KB) - /* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the * SH4. Unlike the SH4 this is a unified cache so we need to do some work * in mmap when 'exec'ing a new binary @@ -48,23 +30,7 @@ void flush_dcache_page(struct page *pg); void flush_icache_range(unsigned long start, unsigned long end); void flush_icache_page(struct vm_area_struct *vma, struct page *page); #else -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define flush_dcache_page(page) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) +#include <cpu-common/cpu/cacheflush.h> #endif -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) - -/* SH3 has unified cache so no special action needed here */ -#define flush_cache_sigtramp(vaddr) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) - -#define p3_cache_init() do { } while (0) - #endif /* __ASM_CPU_SH3_CACHEFLUSH_H */ diff --git a/arch/sh/include/cpu-sh3/cpu/rtc.h b/arch/sh/include/cpu-sh3/cpu/rtc.h deleted file mode 100644 index 319404aaee37..000000000000 --- a/arch/sh/include/cpu-sh3/cpu/rtc.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_SH_CPU_SH3_RTC_H -#define __ASM_SH_CPU_SH3_RTC_H - -#define rtc_reg_size sizeof(u16) -#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */ -#define RTC_DEF_CAPABILITIES 0UL - -#endif /* __ASM_SH_CPU_SH3_RTC_H */ diff --git a/arch/sh/include/cpu-sh3/cpu/sigcontext.h b/arch/sh/include/cpu-sh3/cpu/sigcontext.h deleted file mode 100644 index 17310dc03dcd..000000000000 --- a/arch/sh/include/cpu-sh3/cpu/sigcontext.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __ASM_CPU_SH3_SIGCONTEXT_H -#define __ASM_CPU_SH3_SIGCONTEXT_H - -struct sigcontext { - unsigned long oldmask; - - /* CPU registers */ - unsigned long sc_regs[16]; - unsigned long sc_pc; - unsigned long sc_pr; - unsigned long sc_sr; - unsigned long sc_gbr; - unsigned long sc_mach; - unsigned long sc_macl; -}; - -#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */ diff --git a/arch/sh/include/cpu-sh5/cpu/timer.h b/arch/sh/include/cpu-sh5/cpu/timer.h deleted file mode 100644 index 88da9b341a36..000000000000 --- a/arch/sh/include/cpu-sh5/cpu/timer.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASM_SH_CPU_SH5_TIMER_H -#define __ASM_SH_CPU_SH5_TIMER_H - -#endif /* __ASM_SH_CPU_SH5_TIMER_H */ |