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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-13 10:42:57 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-13 10:44:22 -0700 |
| commit | 7fccd723912702acfc2d75e8f0596982534f7f24 (patch) | |
| tree | ba0de94fae80c24fcf3fa275645cd239b9833b3a /arch | |
| parent | dc5cb7a833e83a0d51373ba7d96e2ed8e1890944 (diff) | |
| parent | efa310ba00716d7a872bdc5fa1f5545edc9efd69 (diff) | |
| download | linux-stable-7fccd723912702acfc2d75e8f0596982534f7f24.tar.gz linux-stable-7fccd723912702acfc2d75e8f0596982534f7f24.tar.bz2 linux-stable-7fccd723912702acfc2d75e8f0596982534f7f24.zip | |
Merge tag 'dt-fixes-for-palmer-5.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes
Microchip RISC-V devicetree fixes for 5.19-rc6
A single fix for mpfs.dtsi:
- The l2 cache controller was never hooked up in the dt, so userspace
is presented with the wrong topology information, so it has been
hooked up.
* tag 'dt-fixes-for-palmer-5.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
riscv: dts: microchip: hook up the mpfs' l2cache
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 3095d08453a1..496d3b7642bd 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -50,6 +50,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu1_intc: interrupt-controller { @@ -77,6 +78,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu2_intc: interrupt-controller { @@ -104,6 +106,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu3_intc: interrupt-controller { @@ -131,6 +134,7 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; |