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| author | Vincenzo Frascino <vincenzo.frascino@arm.com> | 2020-11-30 17:07:09 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-11-30 17:36:52 +0000 |
| commit | 9e5344e0ffc33f4fee899f98b6939a0682b1d9c3 (patch) | |
| tree | 970300df985bfb413a8cdb7b82f660ff41ddf367 /arch | |
| parent | 2a9b3e6ac69a8bf177d8496a11e749e2dc72fa22 (diff) | |
| download | linux-stable-9e5344e0ffc33f4fee899f98b6939a0682b1d9c3.tar.gz linux-stable-9e5344e0ffc33f4fee899f98b6939a0682b1d9c3.tar.bz2 linux-stable-9e5344e0ffc33f4fee899f98b6939a0682b1d9c3.zip | |
arm64: mte: Fix typo in macro definition
UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing
compilation issues when trying to implement in kernel MTE async
mode.
Fix the macro correcting the typo.
Note: MTE async mode will be introduced with a future series.
Fixes: c058b1c4a5ea ("arm64: mte: system register definitions")
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20201130170709.22309-1-vincenzo.frascino@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 174817ba119c..c8ab9900293f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -983,7 +983,7 @@ #define SYS_TFSR_EL1_TF0_SHIFT 0 #define SYS_TFSR_EL1_TF1_SHIFT 1 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) -#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT) +#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) |