diff options
author | Maciej W. Rozycki <macro@linux-mips.org> | 2018-10-08 01:37:07 +0100 |
---|---|---|
committer | Paul Burton <paul.burton@mips.com> | 2018-10-09 10:42:40 -0700 |
commit | a711d43cbbaa4800a15885c1044348982b6c0c4b (patch) | |
tree | c65c1fb975a5ac4e84cdc780c97de3c3f5e6ab9a /arch | |
parent | 4ae0452bddca8b59e9258759123a652161d07871 (diff) | |
download | linux-stable-a711d43cbbaa4800a15885c1044348982b6c0c4b.tar.gz linux-stable-a711d43cbbaa4800a15885c1044348982b6c0c4b.tar.bz2 linux-stable-a711d43cbbaa4800a15885c1044348982b6c0c4b.zip |
MIPS: Correct `mmiowb' barrier for `wbflush' platforms
Redefine `mmiowb' in terms of `iobarrier_w' so that it works correctly
for MIPS I platforms, which have no SYNC machine instruction and use a
call to `wbflush' instead.
This doesn't change the semantics for CONFIG_CPU_CAVIUM_OCTEON, because
`iobarrier_w' expands to `wmb', which is ultimately the same as the
current arrangement. For MIPS I platforms this not only makes any code
that would happen to use `mmiowb' build and run, but it actually
enforces the ordering required as well, as `iobarrier_w' has it already
covered with the use of `wmb'.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20863/
Cc: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/include/asm/io.h | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 312eeed7c5bd..65d2a4d481fc 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -97,6 +97,9 @@ static inline void set_io_port_base(unsigned long base) #define iobarrier_w() wmb() #define iobarrier_sync() iob() +/* Some callers use this older API instead. */ +#define mmiowb() iobarrier_w() + /* * virt_to_phys - map virtual addresses to physical * @address: address to remap @@ -545,14 +548,6 @@ BUILDSTRING(l, u32) BUILDSTRING(q, u64) #endif - -#ifdef CONFIG_CPU_CAVIUM_OCTEON -#define mmiowb() wmb() -#else -/* Depends on MIPS II instruction set */ -#define mmiowb() asm volatile ("sync" ::: "memory") -#endif - static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) { memset((void __force *) addr, val, count); |