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author | Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> | 2022-04-29 13:58:43 +0100 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-06-09 10:23:29 +0200 |
commit | c465cf934bb1c2b63b09b8ebb7dd8730b030f131 (patch) | |
tree | 82f5c47ed335f4db6672c4fa597949568db77397 /arch | |
parent | 977cc97b2e50904e9c5d62059cf46ba466e080b1 (diff) | |
download | linux-stable-c465cf934bb1c2b63b09b8ebb7dd8730b030f131.tar.gz linux-stable-c465cf934bb1c2b63b09b8ebb7dd8730b030f131.tar.bz2 linux-stable-c465cf934bb1c2b63b09b8ebb7dd8730b030f131.zip |
arm64: tegra: Add missing DFLL reset on Tegra210
commit 0017f2c856e21bb900be88469e15dac4f41f4065 upstream.
Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling
clocks") removed deassertion of reset lines when enabling peripheral
clocks. This breaks the initialization of the DFLL driver which relied
on this behaviour.
In order to be able to fix this, add the corresponding reset to the DT.
Tested on Google Pixel C.
Cc: stable@vger.kernel.org
Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 26b3f98a211c..f88dc820389b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1355,8 +1355,9 @@ <&tegra_car TEGRA210_CLK_DFLL_REF>, <&tegra_car TEGRA210_CLK_I2C5>; clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; - reset-names = "dvco"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, + <&tegra_car 155>; + reset-names = "dvco", "dfll"; #clock-cells = <0>; clock-output-names = "dfllCPU_out"; status = "disabled"; |