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author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-24 07:07:45 -0800 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-24 07:07:45 -0800 |
commit | d7e76ce7b76e104936d0898080b1255a848ea0b1 (patch) | |
tree | 3c4e85ccb46a235407c9af3d3b8424561f13cb37 /arch | |
parent | e2d6b54b935a98c7d83f7e27597738be903d6703 (diff) | |
parent | 7df1ff5a5cd615815bc6fb4a3a981e9746935e59 (diff) | |
download | linux-stable-d7e76ce7b76e104936d0898080b1255a848ea0b1.tar.gz linux-stable-d7e76ce7b76e104936d0898080b1255a848ea0b1.tar.bz2 linux-stable-d7e76ce7b76e104936d0898080b1255a848ea0b1.zip |
Merge patch series "riscv: Increase mmap_rnd_bits_max on Sv48/57"
Sami Tolvanen <samitolvanen@google.com> says:
We noticed that 64-bit RISC-V kernels limit mmap_rnd_bits to 24
even if the hardware supports a larger virtual address space size
[1]. These two patches allow mmap_rnd_bits_max to be changed during
init, and bumps up the maximum randomness if we end up setting up
4/5-level paging at boot.
* b4-shazam-merge:
riscv: mm: Update mmap_rnd_bits_max
mm: Change mmap_rnd_bits_max to __ro_after_init
Link: https://lore.kernel.org/r/20230929211155.3910949-4-samitolvanen@google.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv/mm/init.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 32cad6a65ccd..c55915554836 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -767,6 +767,11 @@ static int __init print_no5lvl(char *p) } early_param("no5lvl", print_no5lvl); +static void __init set_mmap_rnd_bits_max(void) +{ + mmap_rnd_bits_max = MMAP_VA_BITS - PAGE_SHIFT - 3; +} + /* * There is a simple way to determine if 4-level is supported by the * underlying hardware: establish 1:1 mapping in 4-level page table mode @@ -1081,6 +1086,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) set_satp_mode(dtb_pa); + set_mmap_rnd_bits_max(); #endif /* |