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| author | Arnd Bergmann <arnd@arndb.de> | 2023-08-17 00:23:34 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-09-01 09:07:44 -0700 |
| commit | eb746180132a555da8cfb02d98cb6d0a9d58e870 (patch) | |
| tree | 7a13de90b7e8c4403b3ca2ca9b92112b5de03246 /arch | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
| download | linux-stable-eb746180132a555da8cfb02d98cb6d0a9d58e870.tar.gz linux-stable-eb746180132a555da8cfb02d98cb6d0a9d58e870.tar.bz2 linux-stable-eb746180132a555da8cfb02d98cb6d0a9d58e870.zip | |
riscv: dma-mapping: only invalidate after DMA, not flush
No other architecture intentionally writes back dirty cache lines into
a buffer that a device has just finished writing into. If the cache is
clean, this has no effect at all, but if a cacheline in the buffer has
actually been written by the CPU, there is a driver bug that is likely
made worse by overwriting that buffer.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20230816232336.164413-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/mm/dma-noncoherent.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index d51a75864e53..94614cf61cdd 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -42,7 +42,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, break; case DMA_FROM_DEVICE: case DMA_BIDIRECTIONAL: - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); break; default: break; |