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| author | Alexander A. Klimov <grandmaster@al2klimov.de> | 2020-07-14 21:12:26 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-07-16 10:52:35 +0200 |
| commit | ef054ad38825c9f027bfdc184fe4b47b46f48831 (patch) | |
| tree | fc2370ddd16e81645ded0ffac348913e07d7398e /arch | |
| parent | 770a697c45de1b40391c4fc0e6350135563e97a7 (diff) | |
| download | linux-stable-ef054ad38825c9f027bfdc184fe4b47b46f48831.tar.gz linux-stable-ef054ad38825c9f027bfdc184fe4b47b46f48831.tar.bz2 linux-stable-ef054ad38825c9f027bfdc184fe4b47b46f48831.zip | |
mips: Replace HTTP links with HTTPS ones
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/Kconfig | 2 | ||||
| -rw-r--r-- | arch/mips/include/asm/war.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6fee1a133e9d..eaf7519e3033 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2825,7 +2825,7 @@ config SMP Y to "Enhanced Real Time Clock Support", below. See also the SMP-HOWTO available at - <http://www.tldp.org/docs.html#howto>. + <https://www.tldp.org/docs.html#howto>. If you don't know what to do here, say N. diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index 1eedd596a064..e43f800e662d 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h @@ -121,7 +121,7 @@ * operate correctly if the internal data cache refill buffer is empty. These * CACHE instructions should be separated from any potential data cache miss * by a load instruction to an uncached address to empty the response buffer." - * (Revision 2.0 device errata from IDT available on http://www.idt.com/ + * (Revision 2.0 device errata from IDT available on https://www.idt.com/ * in .pdf format.) */ #ifndef R4600_V2_HIT_CACHEOP_WAR |