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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-06-30 16:50:43 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-13 09:43:34 +0200 |
| commit | e9d66bdbc5abecaf705bf5a2f4f6279b9e313b0c (patch) | |
| tree | dd9bc23170b2d3ce6fb4be8195cf99b6d19548b0 /crypto/aead.c | |
| parent | 7ebaa41047738d46fca6376b3f1765ef69c463c5 (diff) | |
| download | linux-stable-e9d66bdbc5abecaf705bf5a2f4f6279b9e313b0c.tar.gz linux-stable-e9d66bdbc5abecaf705bf5a2f4f6279b9e313b0c.tar.bz2 linux-stable-e9d66bdbc5abecaf705bf5a2f4f6279b9e313b0c.zip | |
pinctrl: renesas: r8a77995: Add bias pinconf support
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and
pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using
some parts from the common R-Car bias handling, which requires making
rcar_pin_to_bias_reg() public.
R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE#
(GP_3_1) pins. Unlike all other pins, they are controlled by different
bits in the LSI pin pull-up/down control register (PUD2) than in the LSI
pin pull-enable register (PUEN2).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
Diffstat (limited to 'crypto/aead.c')
0 files changed, 0 insertions, 0 deletions