diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-09-29 08:38:50 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-05 13:44:34 +0200 |
| commit | d2692ed490e680a41401cef879adebcfafb4298f (patch) | |
| tree | 046899bf081cf551149a865dac5545e854f1ccb2 /drivers/base/power | |
| parent | 549f4ae2601f968e2474c6031fb4799468882f64 (diff) | |
| download | linux-stable-d2692ed490e680a41401cef879adebcfafb4298f.tar.gz linux-stable-d2692ed490e680a41401cef879adebcfafb4298f.tar.bz2 linux-stable-d2692ed490e680a41401cef879adebcfafb4298f.zip | |
clk: renesas: rzg2l: Lock around writes to mux register
The SD MUX output (SD0) is further divided by 4 in G2{L,UL}. The
divided clock is SD0_DIV4. SD0_DIV4 is registered with
CLK_SET_RATE_PARENT which means a rate request for it is propagated to
the MUX and could reach rzg2l_cpg_sd_clk_mux_set_parent() concurrently
with the users of SD0.
Add proper locking to avoid concurrent accesses on SD MUX set rate
registers.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-4-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/base/power')
0 files changed, 0 insertions, 0 deletions