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authorLinus Torvalds <torvalds@linux-foundation.org>2018-02-01 16:35:31 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2018-02-01 16:35:31 -0800
commitfe53d1443a146326b49d57fe6336b5c2a725223f (patch)
tree0bb6de8614bec52f025a0608910e80d6e9315245 /drivers/bus
parentadbc128fa8b4e9ecfdd11d5dd0a7d9845c6ea510 (diff)
parent796543a64ebffdb638a22f428c4dadd037e34866 (diff)
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann: "A number of new drivers get added this time, along with many low-priority bugfixes. The most interesting changes by subsystem are: bus drivers: - Updates to the Broadcom bus interface driver to support newer SoC types - The TI OMAP sysc driver now supports updated DT bindings memory controllers: - A new driver for Tegra186 gets added - A new driver for the ti-emif sram, to allow relocating suspend/resume handlers there SoC specific: - A new driver for Qualcomm QMI, the interface to the modem on MSM SoCs - A new driver for power domains on the actions S700 SoC - A driver for the Xilinx Zynq VCU logicoreIP reset controllers: - A new driver for Amlogic Meson-AGX - various bug fixes tee subsystem: - A new user interface got added to enable asynchronous communication with the TEE supplicant. - A new method of using user space memory for communication with the TEE is added" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (84 commits) of: platform: fix OF node refcount leak soc: fsl: guts: Add a NULL check for devm_kasprintf() bus: ti-sysc: Fix smartreflex sysc mask psci: add CPU_IDLE dependency soc: xilinx: Fix Kconfig alignment soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu soc: bcm: brcmstb: Be multi-platform compatible soc: brcmstb: biuctrl: exit without warning on non brcmstb platforms Revert "soc: brcmstb: Only register SoC device on STB platforms" bus: omap: add MODULE_LICENSE tags soc: brcmstb: Only register SoC device on STB platforms tee: shm: Potential NULL dereference calling tee_shm_register() soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver soc: xilinx: Create folder structure for soc specific drivers of: platform: populate /firmware/ node from of_platform_default_populate_init() soc: samsung: Add SPDX license identifiers soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe() tee: shm: don't put_page on null shm->pages ...
Diffstat (limited to 'drivers/bus')
-rw-r--r--drivers/bus/omap_l3_noc.c5
-rw-r--r--drivers/bus/omap_l3_smx.c6
-rw-r--r--drivers/bus/ti-sysc.c485
3 files changed, 469 insertions, 27 deletions
diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c
index 5012e3ad1225..b040447575ad 100644
--- a/drivers/bus/omap_l3_noc.c
+++ b/drivers/bus/omap_l3_noc.c
@@ -375,3 +375,8 @@ static void __exit omap_l3_exit(void)
platform_driver_unregister(&omap_l3_driver);
}
module_exit(omap_l3_exit);
+
+MODULE_AUTHOR("Santosh Shilimkar");
+MODULE_AUTHOR("Sricharan R");
+MODULE_DESCRIPTION("OMAP L3 Interconnect error handling driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/bus/omap_l3_smx.c b/drivers/bus/omap_l3_smx.c
index 360a5c0a4ee0..b853a729537a 100644
--- a/drivers/bus/omap_l3_smx.c
+++ b/drivers/bus/omap_l3_smx.c
@@ -309,3 +309,9 @@ static void __exit omap3_l3_exit(void)
platform_driver_unregister(&omap3_l3_driver);
}
module_exit(omap3_l3_exit);
+
+MODULE_AUTHOR("Felipe Balbi");
+MODULE_AUTHOR("Santosh Shilimkar");
+MODULE_AUTHOR("Sricharan R");
+MODULE_DESCRIPTION("OMAP3XXX L3 Interconnect Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index c3c76a1ea8a8..4d46003c46cf 100644
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -18,6 +18,9 @@
#include <linux/pm_runtime.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/platform_data/ti-sysc.h>
+
+#include <dt-bindings/bus/ti-sysc.h>
enum sysc_registers {
SYSC_REVISION,
@@ -36,6 +39,9 @@ enum sysc_clocks {
static const char * const clock_names[] = { "fck", "ick", };
+#define SYSC_IDLEMODE_MASK 3
+#define SYSC_CLOCKACTIVITY_MASK 3
+
/**
* struct sysc - TI sysc interconnect target module registers and capabilities
* @dev: struct device pointer
@@ -45,6 +51,10 @@ static const char * const clock_names[] = { "fck", "ick", };
* @offsets: register offsets from module base
* @clocks: clocks used by the interconnect target module
* @legacy_mode: configured for legacy mode if set
+ * @cap: interconnect target module capabilities
+ * @cfg: interconnect target module configuration
+ * @name: name if available
+ * @revision: interconnect target module revision
*/
struct sysc {
struct device *dev;
@@ -54,12 +64,34 @@ struct sysc {
int offsets[SYSC_MAX_REGS];
struct clk *clocks[SYSC_MAX_CLOCKS];
const char *legacy_mode;
+ const struct sysc_capabilities *cap;
+ struct sysc_config cfg;
+ const char *name;
+ u32 revision;
};
+static u32 sysc_read(struct sysc *ddata, int offset)
+{
+ if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
+ u32 val;
+
+ val = readw_relaxed(ddata->module_va + offset);
+ val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
+
+ return val;
+ }
+
+ return readl_relaxed(ddata->module_va + offset);
+}
+
static u32 sysc_read_revision(struct sysc *ddata)
{
- return readl_relaxed(ddata->module_va +
- ddata->offsets[SYSC_REVISION]);
+ int offset = ddata->offsets[SYSC_REVISION];
+
+ if (offset < 0)
+ return 0;
+
+ return sysc_read(ddata, offset);
}
static int sysc_get_one_clock(struct sysc *ddata,
@@ -206,6 +238,21 @@ static int sysc_check_children(struct sysc *ddata)
return 0;
}
+/*
+ * So far only I2C uses 16-bit read access with clockactivity with revision
+ * in two registers with stride of 4. We can detect this based on the rev
+ * register size to configure things far enough to be able to properly read
+ * the revision register.
+ */
+static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
+{
+ if (resource_size(res) == 8) {
+ dev_dbg(ddata->dev,
+ "enabling 16-bit and clockactivity quirks\n");
+ ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
+ }
+}
+
/**
* sysc_parse_one - parses the interconnect target module registers
* @ddata: device driver data
@@ -236,6 +283,8 @@ static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
}
ddata->offsets[reg] = res->start - ddata->module_pa;
+ if (reg == SYSC_REVISION)
+ sysc_check_quirk_16bit(ddata, res);
return 0;
}
@@ -369,22 +418,12 @@ static int sysc_map_and_check_registers(struct sysc *ddata)
*/
static int sysc_show_rev(char *bufp, struct sysc *ddata)
{
- int error, len;
+ int len;
if (ddata->offsets[SYSC_REVISION] < 0)
return sprintf(bufp, ":NA");
- error = pm_runtime_get_sync(ddata->dev);
- if (error < 0) {
- pm_runtime_put_noidle(ddata->dev);
-
- return 0;
- }
-
- len = sprintf(bufp, ":%08x", sysc_read_revision(ddata));
-
- pm_runtime_mark_last_busy(ddata->dev);
- pm_runtime_put_autosuspend(ddata->dev);
+ len = sprintf(bufp, ":%08x", ddata->revision);
return len;
}
@@ -464,6 +503,151 @@ static const struct dev_pm_ops sysc_pm_ops = {
NULL)
};
+/* At this point the module is configured enough to read the revision */
+static int sysc_init_module(struct sysc *ddata)
+{
+ int error;
+
+ error = pm_runtime_get_sync(ddata->dev);
+ if (error < 0) {
+ pm_runtime_put_noidle(ddata->dev);
+
+ return 0;
+ }
+ ddata->revision = sysc_read_revision(ddata);
+ pm_runtime_put_sync(ddata->dev);
+
+ return 0;
+}
+
+static int sysc_init_sysc_mask(struct sysc *ddata)
+{
+ struct device_node *np = ddata->dev->of_node;
+ int error;
+ u32 val;
+
+ error = of_property_read_u32(np, "ti,sysc-mask", &val);
+ if (error)
+ return 0;
+
+ if (val)
+ ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
+ else
+ ddata->cfg.sysc_val = ddata->cap->sysc_mask;
+
+ return 0;
+}
+
+static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
+ const char *name)
+{
+ struct device_node *np = ddata->dev->of_node;
+ struct property *prop;
+ const __be32 *p;
+ u32 val;
+
+ of_property_for_each_u32(np, name, prop, p, val) {
+ if (val >= SYSC_NR_IDLEMODES) {
+ dev_err(ddata->dev, "invalid idlemode: %i\n", val);
+ return -EINVAL;
+ }
+ *idlemodes |= (1 << val);
+ }
+
+ return 0;
+}
+
+static int sysc_init_idlemodes(struct sysc *ddata)
+{
+ int error;
+
+ error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
+ "ti,sysc-midle");
+ if (error)
+ return error;
+
+ error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
+ "ti,sysc-sidle");
+ if (error)
+ return error;
+
+ return 0;
+}
+
+/*
+ * Only some devices on omap4 and later have SYSCONFIG reset done
+ * bit. We can detect this if there is no SYSSTATUS at all, or the
+ * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
+ * have multiple bits for the child devices like OHCI and EHCI.
+ * Depends on SYSC being parsed first.
+ */
+static int sysc_init_syss_mask(struct sysc *ddata)
+{
+ struct device_node *np = ddata->dev->of_node;
+ int error;
+ u32 val;
+
+ error = of_property_read_u32(np, "ti,syss-mask", &val);
+ if (error) {
+ if ((ddata->cap->type == TI_SYSC_OMAP4 ||
+ ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
+ (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
+ ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
+
+ return 0;
+ }
+
+ if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
+ ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
+
+ ddata->cfg.syss_mask = val;
+
+ return 0;
+}
+
+/* Device tree configured quirks */
+struct sysc_dts_quirk {
+ const char *name;
+ u32 mask;
+};
+
+static const struct sysc_dts_quirk sysc_dts_quirks[] = {
+ { .name = "ti,no-idle-on-init",
+ .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
+ { .name = "ti,no-reset-on-init",
+ .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
+};
+
+static int sysc_init_dts_quirks(struct sysc *ddata)
+{
+ struct device_node *np = ddata->dev->of_node;
+ const struct property *prop;
+ int i, len, error;
+ u32 val;
+
+ ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
+
+ for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
+ prop = of_get_property(np, sysc_dts_quirks[i].name, &len);
+ if (!prop)
+ break;
+
+ ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
+ }
+
+ error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
+ if (!error) {
+ if (val > 255) {
+ dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
+ val);
+ }
+
+ ddata->cfg.srst_udelay = (u8)val;
+ }
+
+ return 0;
+}
+
static void sysc_unprepare(struct sysc *ddata)
{
int i;
@@ -474,9 +658,230 @@ static void sysc_unprepare(struct sysc *ddata)
}
}
+/*
+ * Common sysc register bits found on omap2, also known as type1
+ */
+static const struct sysc_regbits sysc_regbits_omap2 = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = 12,
+ .sidle_shift = 3,
+ .clkact_shift = 8,
+ .emufree_shift = 5,
+ .enwkup_shift = 2,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+};
+
+static const struct sysc_capabilities sysc_omap2 = {
+ .type = TI_SYSC_OMAP2,
+ .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap2,
+};
+
+/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
+static const struct sysc_capabilities sysc_omap2_timer = {
+ .type = TI_SYSC_OMAP2_TIMER,
+ .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap2,
+ .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
+};
+
+/*
+ * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
+ * with different sidle position
+ */
+static const struct sysc_regbits sysc_regbits_omap3_sham = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 4,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+ .emufree_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap3_sham = {
+ .type = TI_SYSC_OMAP3_SHAM,
+ .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap3_sham,
+};
+
+/*
+ * AES register bits found on omap3 and later, a variant of
+ * sysc_regbits_omap2 with different sidle position
+ */
+static const struct sysc_regbits sysc_regbits_omap3_aes = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 6,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = 1,
+ .autoidle_shift = 0,
+ .emufree_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap3_aes = {
+ .type = TI_SYSC_OMAP3_AES,
+ .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
+ .regbits = &sysc_regbits_omap3_aes,
+};
+
+/*
+ * Common sysc register bits found on omap4, also known as type2
+ */
+static const struct sysc_regbits sysc_regbits_omap4 = {
+ .dmadisable_shift = 16,
+ .midle_shift = 4,
+ .sidle_shift = 2,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .emufree_shift = 1,
+ .srst_shift = 0,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4 = {
+ .type = TI_SYSC_OMAP4,
+ .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET,
+ .regbits = &sysc_regbits_omap4,
+};
+
+static const struct sysc_capabilities sysc_omap4_timer = {
+ .type = TI_SYSC_OMAP4_TIMER,
+ .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
+ SYSC_OMAP4_SOFTRESET,
+ .regbits = &sysc_regbits_omap4,
+};
+
+/*
+ * Common sysc register bits found on omap4, also known as type3
+ */
+static const struct sysc_regbits sysc_regbits_omap4_simple = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = 2,
+ .sidle_shift = 0,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4_simple = {
+ .type = TI_SYSC_OMAP4_SIMPLE,
+ .regbits = &sysc_regbits_omap4_simple,
+};
+
+/*
+ * SmartReflex sysc found on omap34xx
+ */
+static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = -ENODEV,
+ .clkact_shift = 20,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_34xx_sr = {
+ .type = TI_SYSC_OMAP34XX_SR,
+ .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
+ .regbits = &sysc_regbits_omap34xx_sr,
+ .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED,
+};
+
+/*
+ * SmartReflex sysc found on omap36xx and later
+ */
+static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 24,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = 26,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_36xx_sr = {
+ .type = TI_SYSC_OMAP36XX_SR,
+ .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
+ .regbits = &sysc_regbits_omap36xx_sr,
+ .mod_quirks = SYSC_QUIRK_UNCACHED,
+};
+
+static const struct sysc_capabilities sysc_omap4_sr = {
+ .type = TI_SYSC_OMAP4_SR,
+ .regbits = &sysc_regbits_omap36xx_sr,
+};
+
+/*
+ * McASP register bits found on omap4 and later
+ */
+static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 0,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = -ENODEV,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4_mcasp = {
+ .type = TI_SYSC_OMAP4_MCASP,
+ .regbits = &sysc_regbits_omap4_mcasp,
+};
+
+/*
+ * FS USB host found on omap4 and later
+ */
+static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = 24,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = 26,
+ .srst_shift = -ENODEV,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
+ .type = TI_SYSC_OMAP4_USB_HOST_FS,
+ .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
+ .regbits = &sysc_regbits_omap4_usb_host_fs,
+};
+
+static int sysc_init_match(struct sysc *ddata)
+{
+ const struct sysc_capabilities *cap;
+
+ cap = of_device_get_match_data(ddata->dev);
+ if (!cap)
+ return -EINVAL;
+
+ ddata->cap = cap;
+ if (ddata->cap)
+ ddata->cfg.quirks |= ddata->cap->mod_quirks;
+
+ return 0;
+}
+
static int sysc_probe(struct platform_device *pdev)
{
- struct device_node *np = pdev->dev.of_node;
struct sysc *ddata;
int error;
@@ -485,7 +890,15 @@ static int sysc_probe(struct platform_device *pdev)
return -ENOMEM;
ddata->dev = &pdev->dev;
- ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
+ platform_set_drvdata(pdev, ddata);
+
+ error = sysc_init_match(ddata);
+ if (error)
+ return error;
+
+ error = sysc_init_dts_quirks(ddata);
+ if (error)
+ goto unprepare;
error = sysc_get_clocks(ddata);
if (error)
@@ -495,9 +908,24 @@ static int sysc_probe(struct platform_device *pdev)
if (error)
goto unprepare;
- platform_set_drvdata(pdev, ddata);
+ error = sysc_init_sysc_mask(ddata);
+ if (error)
+ goto unprepare;
+
+ error = sysc_init_idlemodes(ddata);
+ if (error)
+ goto unprepare;
+
+ error = sysc_init_syss_mask(ddata);
+ if (error)
+ goto unprepare;
pm_runtime_enable(ddata->dev);
+
+ error = sysc_init_module(ddata);
+ if (error)
+ goto unprepare;
+
error = pm_runtime_get_sync(ddata->dev);
if (error < 0) {
pm_runtime_put_noidle(ddata->dev);
@@ -554,16 +982,19 @@ unprepare:
}
static const struct of_device_id sysc_match[] = {
- { .compatible = "ti,sysc-omap2" },
- { .compatible = "ti,sysc-omap4" },
- { .compatible = "ti,sysc-omap4-simple" },
- { .compatible = "ti,sysc-omap3430-sr" },
- { .compatible = "ti,sysc-omap3630-sr" },
- { .compatible = "ti,sysc-omap4-sr" },
- { .compatible = "ti,sysc-omap3-sham" },
- { .compatible = "ti,sysc-omap-aes" },
- { .compatible = "ti,sysc-mcasp" },
- { .compatible = "ti,sysc-usb-host-fs" },
+ { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
+ { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
+ { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
+ { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
+ { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
+ { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
+ { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
+ { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
+ { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
+ { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
+ { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
+ { .compatible = "ti,sysc-usb-host-fs",
+ .data = &sysc_omap4_usb_host_fs, },
{ },
};
MODULE_DEVICE_TABLE(of, sysc_match);