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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-09-12 07:51:31 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-09-18 10:05:02 +0200 |
| commit | becf4a771a12b52dc5b3d2b089598d5603f3bbec (patch) | |
| tree | 234e1042505825a5cdc0a9fb58cc582add0916e4 /drivers/clk/clk-loongson1.c | |
| parent | 17939df3c9acd26e4dac1c5943dd8e58e1bcb4e7 (diff) | |
| download | linux-stable-becf4a771a12b52dc5b3d2b089598d5603f3bbec.tar.gz linux-stable-becf4a771a12b52dc5b3d2b089598d5603f3bbec.tar.bz2 linux-stable-becf4a771a12b52dc5b3d2b089598d5603f3bbec.zip | |
clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()
The bitmask << 16 is anyway set on both branches of if thus move it
before the if and set the lower bits of registers only in case clock is
enabled.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230912045157.177966-12-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/clk-loongson1.c')
0 files changed, 0 insertions, 0 deletions